1. Field of the Invention
The present invention relates to electro-static discharge (ESD) protection devices in semiconductor integrated circuit (IC) devices, and in particular, to ESD protection devices and wells thereunder for the prevention of substrate leakage.
2. Background Art
As products based on ICs become more delicate, they also become more vulnerable to the effects of the external environment, and especially to ESD stress occurring when one pin of an IC is grounded and another pin of the IC contacts an electrostatically-precharged object. Therefore, input pins, output pins, input/output (I/O) pins, and power bus pins for an IC communicating with external systems must be provided with ESD protection devices or circuitry to meet the minimum level of ESD robustness required by commercial applications.
NMOS devices, either with the gate grounded or with the gate coupled to a positive voltage during an ESD event, have commonly been used as primary ESD protection devices for ICs. It is well known that the drain contact of an NMOS device must be kept a few microns apart from the gate of the NMOS device. What is implied is that the drain side of an NMOS device confronting ESD stress in the front line must have a distributed resistor connected in series between the channel under the gate and a coupled pad, and the resistance of the distributed resistor must be larger than an acceptable value. If the ESD transient current starts to localize at a weak spot near the gate, it causes the entire ESD current to rush in, thereby causing local heating and eventually damaging the NMOS device. On the other hand, the distributed resistor helps to raise the potential of the adjacent diffusion area, and hence induce a more uniform ESD current flow towards the whole channel.
It was also known that an n-well layer can be disposed under the contact area of a drain region to avoid Aluminum spiking under a high-heat, high-current, ESD event. However, with the improvements in contact technology, such as using a Tungsten plug, the issue of Aluminum spiking is reduced. On the other hand, the deep n-well is effective in collecting minority carriers (electrons) during a positive-voltage pad-to-VSS ESD event. Unfortunately, due to the intrinsic property of the n-well, the n-well resistance decreases in response to local current/heating which causes local temperature increase, which in turn prompts further reduction of local resistance and increased local current/heating/temperature-rising. As a result, the ESD current flowing in the n-well can be highly non-uniform during an ESD transient. If the n-well is disposed immediately underneath the contacts, the highly non-uniform current flow into the plurality of contacts can cause an adverse effect towards degrading the ESD protection level.
Therefore, there remains a need for an improved ESD protection device that overcomes the drawbacks set forth above.
It is an object of the present invention to provide an improved ESD protection device.
It is another object of the present invention to provide a more effective positioning for N-wells in the P-sub region.
To accomplish the objectives of the present invention, there is provided an electrostatic discharge (ESD) protection device having a semiconductor bulk of a first conductivity type, a first doped region of a second conductivity type formed in the semiconductor bulk, a second doped region of a second conductivity type formed in the semiconductor bulk, a channel region formed between the first doped region and the second doped region, a plurality of contacts formed on the first doped region, and a well of the second conductivity type formed in the semiconductor bulk and positioned between the channel and the contacts. In different embodiments of the present invention, the channel region formed between the first doped region and the second doped region can be formed under by a stripe of field oxide or a gate oxide. One or more islands can be formed on the first doped region.